The present invention relates to a device for converting serial data to parallel data, and for converting parallel data to serial data. It more particularly relates to circuitry which increases the serial data input and output rate of a serial-to-parallel and parallel-to-serial converter.
In data processing systems, there is frequently a need to convert serial data to parallel data or to convert parallel data to serial data. For instance, in many computer peripheral devices, such as tape drives and disk drives, data is sent to and received from the peripheral devices in a serial format. However, data is sent between the processing unit and the memory unit of the computer in a parallel format. Thus, when sending data from the computer to the peripheral device, it is necessary to convert the data from a parallel format to a serial format; and when sending data from the peripheral device to the computer, it is necessary to convert the data from a serial format to a parallel format. Serial-to-parallel and parallel-to-serial converters have been developed to handle the conversion of data between the serial and parallel formats.
The speed at which the computer can send data to or receive data from the peripheral device is limited by the rate at which said data is transmitted and the speed at which the converter can convert data from one format to the other. Thus, the advantages of a high speed peripheral can be defeated by a converter which is slow in converting the data from the serial to parallel or the parallel to serial formats.
U.S. Pat. No. 3,742,456 by McFiggans et al. and issued Jun. 26, 1973 for "Apparatus For Selectively Formatting Serial Data Bits Into Separate Data Characters" discloses an interface apparatus which formats serially received data bits into preassigned groups of bits for transmission to a digital computer.
U.S. Pat. No. 4,284,953 by Hepworth et al. and issued Aug. 18, 1981 for "Character Framing Circuit"discloses a digital logic circuit which includes a shift register for serial loading and parallel unloading of a continuous stream of synchronous serial data characters.
U.S. Pat. No. 4,393,301 by Svendsen and issued Jul. 12, 1983 for "Serial-To-Parallel Converter" discloses a circuit having a plurality of storage means for storing one bit of data, a synchronous counter for counting received consecutive serial data bits, a decoder for sequentially enabling one of the storage means for sequentially storing one data bit, and a parallel clock for simultaneously releasing all of the stored data bits in the form of a parallel word.
U.S. Pat. No. 4,473,879 by Tachiuchi et al. and issued Sep. 25, 1984 for "Data Transfer System In Which Time For Transfer Of Data To A Memory Is Matched To Time Required To Store Data In Memory" discloses a data transfer system having a serial/parallel data converting means, a CPU, and means for making the CPU operation time equal to the transfer time.
U.S. Pat. No. 4,497,041 by Braun and issued Jan. 29, 1985 for "Parallel Serial Controller" discloses a computer-peripheral interface which includes a latch to receive parallel data from a peripheral, a single FIFO memory and a parallel-serial converter for transmission of data to a controlling computer.